Title :
A 40-nm low-power SRAM with multi-stage replica-bitline technique for reducing timing variation
Author :
Komatsu, Shigenobu ; Yamaoka, Masanao ; Morimoto, Masao ; Maeda, Noriaki ; Shimazaki, Yasuhisa ; Osada, Kenichi
Author_Institution :
Central Res. Lab., Hitachi, Ltd., Kokubunji, Japan
Abstract :
A multi-stage replica bitline technique for reducing access time by suppressing enable timing variation of a sense amplifier was developed. Applied to a 288-kbit SRAM of the 40-nm process node, this technique achieves 6.1% access time reduction by reducing the sense-amplifier timing variation by 43%.
Keywords :
SRAM chips; low-power electronics; access time reduction; low-power SRAM; multistage replica bitline technique; sense-amplifier timing variation; size 40 nm; storage capacity 288 Kbit; Circuit stability; Decoding; Degradation; Delay; Logic gates; Random access memory; Testing; Timing; Transistors; Voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 2009. CICC '09. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-4071-9
Electronic_ISBN :
978-1-4244-4073-3
DOI :
10.1109/CICC.2009.5280731
