Title :
Asymmetric sizing in a 45nm 5T SRAM to improve read stability over 6T
Author :
Nalam, Satyanand ; Calhoun, Benton H.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Virginia, Charlottesville, VA, USA
Abstract :
This paper describes a 5-transistor (5T) SRAM bitcell that uses a novel asymmetric sizing approach to achieve increased read stability. Measurements of a 32 kb 5 T SRAM in a 45 nm bulk CMOS technology validate the design, showing read functionality below 0.5 V. The 5 T bitcell has lower write margin than the 6 T, but measurements of the 45 nm 5 T array confirm that a write assist method restores comparable writability with a 6 T down to 0.7 V.
Keywords :
CMOS integrated circuits; SRAM chips; 5-transistor SRAM bitcell; bulk CMOS technology; CMOS technology; Chip scale packaging; Circuit stability; Noise measurement; Noise reduction; Process design; Random access memory; Semiconductor device noise; USA Councils; Writing;
Conference_Titel :
Custom Integrated Circuits Conference, 2009. CICC '09. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-4071-9
Electronic_ISBN :
978-1-4244-4073-3
DOI :
10.1109/CICC.2009.5280733
