Title :
Hardware architecture design for visual processing: present and future
Author :
Tseng, Po-Chih ; Chen, Liang-Gee
Author_Institution :
DSP/IC Design Lab., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
This paper presents the present and future trends of hardware architecture design for image and video coding. Fundamental design issues are discussed with particular emphasis on efficient dedicated implementation. Hardware architectures for MPEG-4 video coding and JPEG 2000 still image coding are reviewed as examples, and special approaches exploited to improve efficiency are identified. Further perspectives are also presented to address the challenges of hardware architecture design for future image and video coding.
Keywords :
VLSI; digital signal processing chips; image coding; system-on-chip; video codecs; video coding; JPEG 2000 coding; MPEG-4 coding; efficient dedicated implementation; hardware architecture design; image coding; video codec; video coding; visual processing; Computer architecture; Hardware; Image coding; MPEG 4 Standard; Memory architecture; Process design; Transform coding; Very large scale integration; Video coding; Videoconference;
Conference_Titel :
Advanced System Integrated Circuits 2004. Proceedings of 2004 IEEE Asia-Pacific Conference on
Print_ISBN :
0-7803-8637-X
DOI :
10.1109/APASIC.2004.1349388
