Title :
System power distribution network theory and performance with various noise current stimuli including impacts on chip level timing
Author :
Smith, Larry ; Sun, Shishuang ; Boyle, Peter ; Krsnik, Bozidar
Author_Institution :
Altera Corp., San Jose, CA, USA
Abstract :
Power Quality has become a determining factor in product performance and reliability. The reactive portions of the power distribution network (PDN) have a greater effect on power quality than DC IR drop. Resonance in the parallel inductance and capacitance network creates an impedance peak in the frequency domain and undesirable voltage noise in the time domain. The on-chip voltage noise is usually much higher than PCB PDN noise. A method of determining and simulating circuit parameters and comparing results to a target impedance is presented. A test vehicle has been built and measured to provide laboratory measured results for PDN voltage noise. Switching current patterns are defined which generate typical and pathological voltage waveforms. PRBS patterns are used as a characterization technique to provide reasonable worst case resonance stimulation. The voltage noise is responsible for measured timing and jitter degradation in logic circuits.
Keywords :
digital integrated circuits; integrated circuit noise; integrated circuit reliability; jitter; logic circuits; monolithic integrated circuits; timing; capacitance network; chip level timing; frequency domain; jitter; logic circuits; noise current stimuli; on-chip voltage noise; parallel inductance network; power distribution network; reliability; switching current patterns; Circuit noise; Network-on-a-chip; Noise level; Noise measurement; Power quality; Power systems; Resonance; System-on-a-chip; Timing; Voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 2009. CICC '09. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-4071-9
Electronic_ISBN :
978-1-4244-4073-3
DOI :
10.1109/CICC.2009.5280742
