Title :
ESD design challenges
Author :
Sachdev, Manoj ; Vuong, Hong-Ha
Author_Institution :
University of Waterloo, Canada
Abstract :
With the scaling of CMOS technology the design of Electro-Static Discharge (ESD) protection circuits is becoming an increasingly challenging task. This challenge is mainly due to thinner gate oxide, shorter channel length, and shallower junctions. In addition, higher operational frequencies necessitate lower parasitic capacitance ESD protection circuits which often compromise the ESD protection level.
Keywords :
CMOS technology; Design automation; Electrostatic discharge; Frequency; Integrated circuit packaging; Integrated circuit technology; Large scale integration; Paper technology; Parasitic capacitance; Protection;
Conference_Titel :
Custom Integrated Circuits Conference, 2009. CICC '09. IEEE
Conference_Location :
San Jose, CA, USA
Print_ISBN :
978-1-4244-4071-9
Electronic_ISBN :
978-1-4244-4073-3
DOI :
10.1109/CICC.2009.5280757
