Design of Low Adder Cost FIR Digital Filters Using Graph Representation

The hardware implementation of digital filters is mainly dominated by the multiplier blocks. Implementing constant coefficient digital FIR filters multiplier block as a network of adders, subtractors, and shifters will achieve lower power consumption. This paper uses the graph representations to reduce designed hardware complexity. To further reduce the adder cost, we enhance the hardware resources sharing of different filter coefficients. Simulation results show that using the proposed method has reduced adder cost of multiplier blocks.