Design of 2xVDD-tolerant I/O buffer with 1xVDD CMOS devices

Author

Ker, Ming-Dou ; Lin, Yan-Liang

Author_Institution

Inst. of Electron., Nat. Chiao-Tung Univ., Hsinchu, Taiwan

fYear

2009

Firstpage

539

Lastpage

542

Abstract

A new 2xVDD-tolerant I/O buffer realized with only 1xVDD devices has been proposed and verified in a 0.18-mum CMOS process. With the dynamic source output technique and the new gate-controlled circuit, the new proposed I/O buffer can transmit and receive the signals with the voltage swing twice as high as the normal power supply voltage (VDD) without suffering gate-oxide reliability problem. The proposed 2xVDD-tolerant I/O circuit solution can be implemented in different nanoscale CMOS processes to meet the mixed-voltage interface applications in microelectronic systems.

Keywords

CMOS integrated circuits; buffer circuits; integrated circuit design; power supply circuits; 1xVDD CMOS devices; 2xVDD-tolerant I/O buffer; CMOS processes; dynamic source output technique; gate-controlled circuit; gate-oxide reliability problem; microelectronic systems; mixed-voltage interface applications; normal power supply voltage; size 0.18 mum; voltage swing; CMOS process; CMOS technology; Circuit synthesis; Low voltage; Microelectronics; Noise reduction; Power supplies; Reliability engineering; Signal design; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2009. CICC '09. IEEE

Conference_Location

San Jose, CA

Print_ISBN

978-1-4244-4071-9

Electronic_ISBN

978-1-4244-4073-3

Type

conf

DOI

10.1109/CICC.2009.5280763

Filename

5280763