Simple test yield evaluation for analog circuits

In this article a simple test yield evaluation model is proposed for analog circuits. This model allows a rapid assessment of any intended test-algorithm in its ability to detect parametric device failures. It uses high level functional modelling of the circuit-under-test incorporating those parameters on which as pass/fail decision is based, and stochastical simulation of this model in conjunction with a given test-scheme to calculate various probabilities such as the fault detection rate and the probability of rejecting a good device or accepting a faulty device (type I and II errors). Such an analysis can give useful insight into the trade-offs involved in the test-process between complexity and parametric coverage. Also, comparisons between different test-schemes are easily made. Furthermore it can be used to optimize the test limits (e.g. guardbanding) with respect to coverage. This will be illustrated with an example of an A/D converter where linearity errors need to be detected by simple data manipulations of the output response