Test evaluation for complex mixed-signal ICs by introducing layout dependent faults

This paper has two aims. Firstly, to give an insight into the techniques used in writing and implementing accurate behavioural models, showing that simple modelling techniques are adequate. Secondly, how these models can be used to implement a fault simulation methodology using IFA techniques for analogue circuits. The test vehicle is a Philips-designed phase-locked-loop (PLL) IC which has a high gate count, is of a mixed signal design, and is unsimulatable in a layout-extracted netlist form. Defect simulation using high-level subcircuit descriptions of the PLL enable standard and novel testing strategies to be evaluated, indicating which method will achieve the highest defect coverage