DocumentCode
1700981
Title
Tera-scale performance machine learning SoC with dual stream processor architecture for multimedia content analysis
Author
Chen, Tse-Wei ; Tang, Chi-Sun ; Tsai, Sung-Fang ; Tsai, Chen-Han ; Chien, Shao-Yi ; Chen, Liang-Gee
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fYear
2009
Firstpage
491
Lastpage
494
Abstract
A new SoC architecture for multimedia content analysis is implemented with 16 mm2 area in 90 nm CMOS technology. It focuses on the co-acceleration of computer vision and machine learning algorithms, and two stream processors with massively parallel processing elements are integrated to achieve tera-scale performance. In the dual processor architecture, the data are transferred between processors and the high bandwidth dual memory through the local media bus, which reduces the power consumption in the AHB data access. The power efficiency of the proposed machine learning SoC is 1.7 TOPS/W, and the area efficiency is 81.3 GOPS/mm2.
Keywords
CMOS integrated circuits; computer vision; multimedia systems; system-on-chip; CMOS technology; SoC; computer vision; dual stream processor architecture; multimedia content analysis; size 90 nm; tera-scale performance machine learning; Bandwidth; CMOS technology; Computer architecture; Computer vision; Energy consumption; Machine learning; Machine learning algorithms; Parallel processing; Performance analysis; Streaming media;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2009. CICC '09. IEEE
Conference_Location
San Jose, CA
Print_ISBN
978-1-4244-4071-9
Electronic_ISBN
978-1-4244-4073-3
Type
conf
DOI
10.1109/CICC.2009.5280791
Filename
5280791
Link To Document