REad/access-preferred (REAP) SRAM - architecture-aware bit cell design for improved yield and lower VMIN

We present an architecture-aware SRAM design that decouples the conflicting requirements between read stability and writeability. Read and hold failures are reduced by preferentially sizing the cell to have better read stability at the expense of write failures (at iso-area). The increased write failures are handled by stretching the write cycle. Measurement results on a 90 nm 2 kb test chip show 80 mV higher weak-write test voltage, 61%, 25% and 500X reduction in hold, read and write failures, respectively, without any increase in access failures. This results in improved yield relative to an iso-area nominal 6T cell, with only 3% loss in performance (based on architecture level simulation) on average.