A word-based RSA crypto-processor with enhanced pipeline performance

Author

Wang, Chen-Hsing ; Su, Chih-Pin ; Huang, Chih-Tsun ; Wu, Cheng-Wen

Author_Institution

Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan

fYear

2004

Firstpage

218

Lastpage

221

Abstract

We propose a high speed RSA crypto-processor based on an enhanced word-based Montgomery Multiplication (MM) algorithm. With the help of the proposed Correction Module (CM), the word-based modular multiplier can achieve 100% utilization. A simplified Parity Prediction Module (PPM) is also proposed to eliminate the pipeline stall. Using a 0.18 μm CMOS standard cell library, our RSA crypto-processor achieves a 512-bit RSA encryption rate of 375Kbps under 300MHz clock. The result shows that our architecture is cost-effective in terms of area and performance.

Keywords

CMOS digital integrated circuits; computational complexity; coprocessors; digital signal processing chips; pipeline arithmetic; public key cryptography; CMOS standard cell; Montgomery multiplication algorithm; correction module; critical path delay; data flow graph; enhanced pipeline performance; hardware architecture; high speed crypto-processor; modular multiplier; public-key cryptographic algorithm; simplified parity-prediction module; time complexity; word-based RSA crypto-processor; Application software; Clocks; Communication system security; Computer architecture; Computer networks; Computer security; Cryptography; Data security; Hardware; Pipelines;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced System Integrated Circuits 2004. Proceedings of 2004 IEEE Asia-Pacific Conference on

Print_ISBN

0-7803-8637-X

Type

conf

DOI

10.1109/APASIC.2004.1349453

Filename

1349453