DocumentCode
1701341
Title
A 2-Gbps CMOS adaptive line equalizer
Author
Lee, Jae-Wook ; Lee, Bhum-Cheol ; Choi, Woo-Young
Author_Institution
Dept. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea
fYear
2004
Firstpage
244
Lastpage
247
Abstract
A 2-Gbps line equalizer circuit is realized with 0.25 μm CMOS technology. The equalizer is made of input stage buffer, limiter and square difference circuits. The limiter has replica-feedback limiting amplifiers, which do not require common mode feedback. Successful equalization is demonstrated for signals transmitted over 1.5m long PCB trace.
Keywords
CMOS analogue integrated circuits; adaptive equalisers; feedback amplifiers; operational amplifiers; transfer functions; 2 Gbit/s; CMOS adaptive line equalizer; attenuation curves; eye diagram; high-rate NRZ data communication; input stage buffer; inverse channel characteristic transfer function; limiter; opamp-based analog equalizer; replica-feedback limiting amplifiers; square difference circuits; Attenuation; CMOS technology; Circuits; Data communication; Decision feedback equalizers; Filtering; Filters; Frequency; Strips; Transfer functions;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced System Integrated Circuits 2004. Proceedings of 2004 IEEE Asia-Pacific Conference on
Print_ISBN
0-7803-8637-X
Type
conf
DOI
10.1109/APASIC.2004.1349461
Filename
1349461
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