Title :
A hardware efficient 64-QAM low-IF transceiver baseband for broadband communications
Author :
Chang, Ching-Chi ; Shiue, Muh-Tian ; Wang, Chomg-Kuang
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
This paper presents a hardware efficient VLSI design of digital baseband for 64-QAM communication systems over the last-mile cable network. This VLSI system design involves a cost-efficient architecture of the adaptive equalizer and a two-phase linear architecture of the pulse shaping filters, which reduce the hardware requirement by a factor of four comparing with traditional quadrature direct form FIR filters. In this design, the two-fold carrier recovery loop possesses a pull-in range of ±100kHz (i.e. ±18, 500ppm of the symbol rate) and -82dBc jitter suppression. Based on the proposed multi-staged LMS-based fractionally-spaced equalizer, the receiver realizes the symbol spaced timing recovery in a ±200ppm tolerance of the symbol rate. The acquisition time of the proposed 64-QAM blind adaptive system is 7ms, and the transceiver reaches the operation speed of the case for 32.28Mb/s 64-QAM low-IF digital CATV system over NTSC 6MHz bandwidth channels. Using 0.35 μm CMOS technology, the transceiver design occupies a chip area 5.5mm × 5.5mm and power consumption 1.35W (1.0W for RX) when the power supply is 3.3V.
Keywords :
CMOS digital integrated circuits; VLSI; adaptive equalisers; broadband networks; cable television; digital television; integrated circuit layout; pulse shaping circuits; quadrature amplitude modulation; synchronisation; timing jitter; transceivers; 1.35 W; 3.3 V; CMOS technology; LMS-based fractionally-spaced equalizer; QAM low-IF transceiver baseband; adaptive equalizer; broadband communications; cost-efficient architecture; digital CATV system; hardware efficient VLSI design; jitter suppression; last-mile digital communication; post-layout extracted circuit; pulse shaping filters; symbol spaced timing recovery; two-fold carrier recovery loop; two-phase linear architecture; Adaptive equalizers; Baseband; Broadband communication; CMOS technology; Communication cables; Finite impulse response filter; Hardware; Pulse shaping methods; Transceivers; Very large scale integration;
Conference_Titel :
Advanced System Integrated Circuits 2004. Proceedings of 2004 IEEE Asia-Pacific Conference on
Print_ISBN :
0-7803-8637-X
DOI :
10.1109/APASIC.2004.1349463