Logic simulation and fault collapsing with shared structurally synthesized bdds

Author

Mironov, Dmitri ; Ubar, Raimund ; Raik, Jaan

Author_Institution

Dept. of Comput. Eng., Tallinn Univ. of Technol., Tallinn, Estonia

fYear

2014

fDate

26-30 May 2014

Firstpage

1

Lastpage

2

Abstract

A new method for logic simulation and fault modeling in combinational circuits with Structurally Synthesized BDDs (SSBDD) is proposed. The new model is constructed by merging different super-graphs (SSBDDs) related to different circuit outputs, which share as much as possible different subgraphs (SSBDDs) representing the circuit. We call this model as Shared SSBDDs (S3_BDD) where each node represents a particular signal path (or segment) of the circuit, and as well the representatives of different fault classes related to this path. A lower bound for the size of the S3_BDD model for a given circuit, a method for synthesis of S3_BDDs with the size close to the lower bound, and a fast logic simulation method based on S3BDDs were developed. Experimental research results support the claims about the efficiency of the model.

Keywords

binary decision diagrams; graph theory; logic simulation; S3_BDD model; binary decision diagrams; circuit outputs; fast logic simulation method; fault collapse; shared structurally synthesized BDD; signal path representation; supergraphs; Analytical models; Boolean functions; Circuit faults; Computational modeling; Data structures; Integrated circuit modeling; Logic gates; Shared Structurally Synthesized Binary Decision Diagrams; digital circuits; fault collapsing; logic models; logic simulation;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium (ETS), 2014 19th IEEE European

Conference_Location

Paderborn

Type

conf

DOI

10.1109/ETS.2014.6847825

Filename

6847825