Trend from ICs to 3D ICs to 3D systems

Author

Tummala, Rao R. ; Sundaram, Venky ; Chatterjee, Ritwik ; Raj, P. Markondeya ; Kumbhat, Nitesh ; Sukumaran, Vijay ; Sridharan, Vivek ; Choudury, Abhishek ; Chen, Qiao ; Bandyopadhyay, Tapobrata

fYear

2009

Firstpage

439

Lastpage

444

Abstract

Moore´s law has driven the IC industry to a billion transistor chip. But major technical and financial barriers are foreseen beyond 32 nm. One alternative path to this challenge seems to be stacked 3D ICs. But 3D ICs are a small part of any system and the total benefits of miniaturization cannot be realized until the entire system is miniaturized. This is the basis of 3D systems, the focus of this paper. The 3D miniaturization technologies briefly described in this paper include Si or wafer level interposers with Through-Package-Vias (TPV), nano-scale passives, thermal materials and interfaces and fine pitch system interconnections.

Keywords

integrated circuit design; integrated circuit interconnections; integrated circuit manufacture; integrated circuit packaging; nanotechnology; semiconductor technology; technological forecasting; 3D systems; Moore law; fine pitch system interconnection; integrated circuit trends; miniaturization technology; nanoscale passives; stacked 3D IC; thermal material; through-package-vias; wafer level interposer; Moore´s Law; Nanostructured materials;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2009. CICC '09. IEEE

Conference_Location

San Jose, CA

Print_ISBN

978-1-4244-4071-9

Electronic_ISBN

978-1-4244-4073-3

Type

conf

DOI

10.1109/CICC.2009.5280817

Filename

5280817