DocumentCode
1701793
Title
A parallel multi-pattern PRBS generator and BER tester for 40+ Gbps Serdes applications
Author
Chen, Wei-Zen ; Huang, Guan-Sheng
Author_Institution
Dept. of Electron. Eng., Nat. Chiao-Tung Univ., Hsin-Chu, Taiwan
fYear
2004
Firstpage
318
Lastpage
321
Abstract
This paper presents the design of a programmable PRBS generator and a BER tester according to CCITT recommendations. Implemented in a parallel feedback configuration, this IC features PRBS generation of the sequences of length 27-1, 210-1, 215-1, 223-1 and 231-1 b for up to 40+Gbps Serdes applications with 1:16 multiplexing and demultiplexing. The mark densities of 1/2, 1/4 and 1/8 for each of the patterns are also selectable. This IC could be used as a low cost substitute for more expensive bit error rate test system. Implemented in a 0.18 μm CMOS process, the total power dissipation is 141 mW.
Keywords
CMOS logic circuits; automatic test pattern generation; binary sequences; built-in self test; error statistics; high-speed integrated circuits; programmable circuits; shift registers; transceivers; BER tester; CCITT recommendations; CMOS process; Parallel multi-pattern PRBS generator; Serdes applications; automatic testing; built-in self test; demultiplexing; generic architecture; high speed transceivers; multiplexing; on chip bit error counting; parallel feedback configuration; parallel feedback shift registers; programmable PRBS generator; pseudo random bit sequences; test pattern generation; Automatic testing; Bit error rate; CMOS technology; Circuit testing; Costs; Electronic equipment testing; Integrated circuit testing; Jitter; System testing; Transceivers;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced System Integrated Circuits 2004. Proceedings of 2004 IEEE Asia-Pacific Conference on
Print_ISBN
0-7803-8637-X
Type
conf
DOI
10.1109/APASIC.2004.1349484
Filename
1349484
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