Title :
A 1.7∼3.125Gbps clock and data recovery circuit using a gated frequency detector
Author :
Yang, Rong-Jyi ; Liu, Shen-Iuan
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
A fully integrated clock and data recovery (CDR) circuit with the proposed gated frequency detector (GFD) is presented. It has been realized in a standard 0.25-μm CMOS technology. The proposed voltage-controlled oscillator (VCO) can achieve wide operation range and small KVCO by employing the analog/digital dual loop architecture. It can relax the constraint on choosing the loop parameter to reduce the size of the on-chip capacitor. The proposed GFD will make the frequency lock time fixed and can avoid the harmonic locking problem for wide data rate operations. All measured BERs are less than 10-12 with the data rate from 1.7Gbps to 3.125Gbps.
Keywords :
CMOS integrated circuits; clocks; data communication equipment; frequency locked loops; mixed analogue-digital integrated circuits; phase detectors; synchronisation; timing jitter; transceivers; voltage-controlled oscillators; 1.7 to 3.125 Gbit/s; clock and data recovery circuit; fixed frequency lock time; fully integrated circuit; gated frequency detector; high speed data communications; high speed transceivers; linear half-rate phase detector; random data; standard CMOS technology; timing diagram; voltage-controlled oscillator; CMOS technology; Charge pumps; Circuits; Clocks; Delay; Detectors; Frequency; Power harmonic filters; Tuning; Voltage-controlled oscillators;
Conference_Titel :
Advanced System Integrated Circuits 2004. Proceedings of 2004 IEEE Asia-Pacific Conference on
Print_ISBN :
0-7803-8637-X
DOI :
10.1109/APASIC.2004.1349486
