Title :
Delay macro modeling of CMOS gates using modified logical effort technique
Author :
Kabbani, A. ; Al-Khalili, D. ; Al-Khalili, A.J.
Author_Institution :
Dept. of ECE, Ryerson Univ., Toronto, Ont., Canada
Abstract :
Modified logical effort (MLE) technique is proposed in this paper to provide delay estimation for CMOS gates. The model accounts for the behavior of series connected MOSFET structure (SCMS), the switching input transition time and internodal charges. Also the model takes into account deep submicron effects such as mobility degradation and velocity saturation. This model exhibits a good accuracy when compared with Spectre simulations using BSIM3v3 model. An average error of 3.1% was obtained based on UMC´s 0.13μm technology.
Keywords :
CMOS logic circuits; delays; integrated circuit modelling; logic gates; 0.13 micron; CMOS gates; deep submicron effects; delay estimation; delay macro modeling; internodal charges; mobility degradation; modified logical effort technique; series connected MOSFET structure; switching input transition time; CMOS logic circuits; Degradation; Delay estimation; Inverters; MOS devices; MOSFET circuits; Maximum likelihood estimation; Parasitic capacitance; Predictive models; Semiconductor device modeling;
Conference_Titel :
Semiconductor Electronics, 2004. ICSE 2004. IEEE International Conference on
Print_ISBN :
0-7803-8658-2
DOI :
10.1109/SMELEC.2004.1620837
