GPU-based timing-aware test generation for small delay defects

Author

Kuan-Yu Liao ; Po-Juei Chen ; Ang-Feng Lin ; Li, James Chien-Mo ; Hsiao, Michael S. ; Laung-Terng Wang

Author_Institution

Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

2014

fDate

26-30 May 2014

Firstpage

1

Lastpage

2

Abstract

A GPU-based timing-aware ATPG is proposed to generate a compact high-quality test set. The test generation algorithm backtraces and propagates along multiple long paths so that many test patterns are generated at the same time. Generated test patterns are then fault simulated and selected. Compared with an 8-core CPU-based timing-aware commercial ATPG, the proposed GPU-based technique achieved 36% test length reductions on large benchmark circuits while the SDQL quality remains almost the same.

Keywords

automatic test pattern generation; delays; graphics processing units; integrated circuit testing; GPU-based timing-aware ATPG; GPU-based timing-aware test generation technique; SDQL quality; benchmark circuits; compact high-quality test set generation; small delay defects; test length reductions; test pattern generation; Automatic test pattern generation; Circuit faults; Delays; Graphics processing units; Integrated circuit modeling; Kernel; Load modeling; GPU; parallel; small delay defect; test generation;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium (ETS), 2014 19th IEEE European

Conference_Location

Paderborn

Type

conf

DOI

10.1109/ETS.2014.6847835

Filename

6847835