Design and Implementation Multilevel Inverter for 3ϕ Induction Motor Speed Control with RBM Chopper Technique embedded on FPGA

This paper introduces on designing of regular-based binary multiplier: RBM signal embedded on field programmable gate array: FPGA, which control induction-motor speed. Various forms of 8-bit RBM signal are generated and choppered with the multilevel-inverter output voltage whose switching angle is provided for determining amplitude of fundamental frequency and eliminating un required low-order harmonics. Objectives of this switching technique is improvement of the inverter output signal in term of total harmonic distortion voltage reduction (%THD) while controlling the motor. Such motor´s efficiency and performance are improved while voltage to frequency ratio is maintained constantly for stable torque during control.