Comparative study of static and dynamic D-type flip-flop circuits using InP HBTs

Author

Hwan-Seok Yeo ; Jinwook Burm

Author_Institution

Dept. of Electron. Eng., Sogang Univ., Seoul, South Korea

fYear

2004

Firstpage

352

Lastpage

355

Abstract

A static and a dynamic D-type flip-flops (D-FFs) using InP heterojunction bipolar transistors (HBTs) were analyzed. Both the static and dynamic D-FFs employed conventional read/latch structure, however the dynamic D-FF had smaller latch current than the read current to improve the bandwidth. The static D-FF exhibited the maximum operating bit rate of 12 Gbit/s with rising/falling time of 67 ps/45 ps. The dynamic D-FF operated up to 20 Gbit/s with rising/falling time of 50 ps/32 ps. A dynamic D-FF exhibited the minimum operating bit rate of 1 Gbit/s.

Keywords

III-V semiconductors; bipolar logic circuits; emitter-coupled logic; equivalent circuits; flip-flops; indium compounds; 12 Gbit/s; 20 Gbit/s; D-type flip-flop circuits; InP; dynamic flip-flop; emitter-coupled logic; heterojunction bipolar transistors; high frequency operation; latch current; pseudorandom bit sequence; read-latch structure; small-signal equivalent circuit; static flip-flop; Bandwidth; Bit rate; Circuits; Clocks; Flip-flops; Frequency; Heterojunction bipolar transistors; Indium phosphide; Latches; Optical fiber networks;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced System Integrated Circuits 2004. Proceedings of 2004 IEEE Asia-Pacific Conference on

Print_ISBN

0-7803-8637-X

Type

conf

DOI

10.1109/APASIC.2004.1349494

Filename

1349494