Aging and voltage scaling impacts under neutron-induced soft error rate in SRAM-based FPGAs

Author

Lima Kastensmidt, Fernanda ; Tonfat, Jorge ; Both, Thomas ; Rech, P. ; Wirth, Glen ; Reis, R. ; Bruguier, Florent ; Benoit, Pascal ; Torres, L. ; Frost, Christopher

Author_Institution

PGMICRO, UFRGS, Porto Alegre, Brazil

fYear

2014

fDate

26-30 May 2014

Firstpage

1

Lastpage

2

Abstract

This work investigates the effects of aging and voltage scaling in neutron-induced bit-flip in SRAM-based FPGAs. Experimental results show that aging and voltage scaling can increase in at least two times the susceptibility of SRAM-based FPGAs to Soft Error Rate (SER). These results are innovative, because they combine three real effects that occur in programmable circuits operating at ground-level applications. In addition, a model at electrical simulation for aging, soft error and different voltages was described to investigate the effects observed at the practical neutron irradiation experiment. Results can guide designers to predict soft error effects during the lifetime of devices operating in different power supply mode.

Keywords

SRAM chips; field programmable gate arrays; power aware computing; SER; SRAM-based FPGA; aging impact; electrical simulation model; field programmable gate arrays; ground-level applications; neutron irradiation experiment; neutron-induced bit-flip; neutron-induced soft error rate; power supply mode; programmable circuits; static random access memory; voltage scaling impact; Aging; Error analysis; Field programmable gate arrays; Neutrons; Power supplies; SRAM cells; Stress; FPGA; aging; radiation; volage scalling;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium (ETS), 2014 19th IEEE European

Conference_Location

Paderborn

Type

conf

DOI

10.1109/ETS.2014.6847845

Filename

6847845