Title :
Fast lock scheme for phase-locked loops
Author :
Bashir, Amir ; Li, Jing ; Ivatury, Kiran ; Khan, Naveed ; Gala, Nirav ; Familia, Noam ; Mohammed, Zulfiqar
Author_Institution :
Intel Corp., Folsom, CA, USA
Abstract :
This paper describes a fast lock scheme for phaselocked loops (PLLs). The proposed scheme utilizes mostly digital logic and control to achieve significant reduction in PLL lock acquisition time, which enables dynamic power cycling for various sub-systems on SOC designs. Multiple Self-Bias PLLs having fast lock schemes were designed to operate at VCO frequencies from 1.6 GHz to 5 GHz, and fabricated using 65 nm CMOS process. Silicon measurements indicate up to 75% reduction in worst-case PLL lock times over the device operating conditions.
Keywords :
CMOS integrated circuits; UHF integrated circuits; phase locked loops; system-on-chip; voltage-controlled oscillators; CMOS process fabrication; PLL lock acquisition time; SOC design; VCO frequency; digital logic; fast lock scheme; frequency 1.6 GHz to 5 GHz; phase-locked loop; size 65 nm; CMOS logic circuits; CMOS process; Digital control; Frequency; Logic design; Phase locked loops; Silicon; Voltage-controlled oscillators;
Conference_Titel :
Custom Integrated Circuits Conference, 2009. CICC '09. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-4071-9
Electronic_ISBN :
978-1-4244-4073-3
DOI :
10.1109/CICC.2009.5280830
