Fast lock scheme for phase-locked loops

This paper describes a fast lock scheme for phaselocked loops (PLLs). The proposed scheme utilizes mostly digital logic and control to achieve significant reduction in PLL lock acquisition time, which enables dynamic power cycling for various sub-systems on SOC designs. Multiple Self-Bias PLLs having fast lock schemes were designed to operate at VCO frequencies from 1.6 GHz to 5 GHz, and fabricated using 65 nm CMOS process. Silicon measurements indicate up to 75% reduction in worst-case PLL lock times over the device operating conditions.