Title :
Analysis of digital bang-bang clock and data recovery for multi-gigabit/s serial transceivers
Author :
Sun, Yehui ; Wang, Hui
Author_Institution :
Integrated Device Technol., Shanghai, China
Abstract :
A harmonic balance method for analyzing digital bang-bang clock and data recovery (CDR) is proposed in this paper. The jitter tolerance performance of the CDR is predicted by a function with variables that can be easily correlated to design parameters. A 6.25 Gb/s serial transceiver was fabricated in 90 nm CMOS technology. Measurements show that the jitter tolerance performance can be accurately predicted by the proposed method.
Keywords :
CMOS digital integrated circuits; clock and data recovery circuits; synchronisation; timing jitter; transceivers; CMOS technology; bit rate 6.25 Gbit/s; data recovery; digital bang-bang clock; harmonic balance method; jitter tolerance; multigigabit serial transceivers; size 90 nm; CMOS technology; Clocks; Harmonic analysis; Jitter; Transceivers;
Conference_Titel :
Custom Integrated Circuits Conference, 2009. CICC '09. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-4071-9
Electronic_ISBN :
978-1-4244-4073-3
DOI :
10.1109/CICC.2009.5280835
