DocumentCode
1702254
Title
The effects of gate oxide short in 6-transistors SRAM cell
Author
A´Ain, Abu Khari B b ; Sin, Sim Kian ; Siong, Heow Kwee
Author_Institution
INSEED, Univ. Teknologi Malaysia, Johor, Malaysia
fYear
2004
Abstract
The effects of gate oxide short (GOS) in a single 6-MOS transistors SRAM cell are studied in this work, through SPICE simulation. Both uni-directional split model and bi-dimensional lumped-transistors model are used to model the GOS in NMOS for comparison. It is assumed that only one NMOS is defective at a time. TSMC 0.18μm process parameters are used in the SPICE simulations. Interesting findings and results showed that GOS may leave catastrophic impacts on SRAM operations.
Keywords
MOS memory circuits; SPICE; SRAM chips; 0.18 micron; MOS transistors; NMOS; SPICE simulation; SRAM cell; gate oxide short; lumped-transistors model; split model; Breakdown voltage; Electronics industry; Impedance; Joining processes; MOS devices; MOSFETs; Random access memory; SPICE; Silicon compounds; Tunneling; GOS; NMOS; SRAM; lumped-transistors model; split model;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Electronics, 2004. ICSE 2004. IEEE International Conference on
Print_ISBN
0-7803-8658-2
Type
conf
DOI
10.1109/SMELEC.2004.1620852
Filename
1620852
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