Digital hardware implementation of bus-based, field-ordered Hopfield network using VHDL

Author

Shiun, Kuek Chian ; Wan Abdullah, Wan Ahmad Tajuddin ; Kamaluddin, Burhanuddin

Author_Institution

Dept. of Phys., Malaya Univ., Kuala Lumpur, Malaysia

fYear

2004

Abstract

This paper presents some new approach in designing hardware discrete Hopfield network. For the network architecture, the bus-based approach is used to largely reduce the number of connection count. Field-ordered updating algorithm is used in place of the typical random-ordered updating due to its added advantage in finding global minimum. As for the implementation, VLSI language has been used due to its ease in describing and documenting complex digital design. Besides, modern CAD tools enables the synthesis of VHDL codes into layout plans on customized FPGA chips and making corresponding timing simulation.

Keywords

Hopfield neural nets; digital circuits; hardware description languages; integrated circuit design; neural nets; Hopfield network; VHDL; VLSI language; bus-based approach; customized FPGA chips; digital design; field-ordered updating; modern CAD tools; network architecture; timing simulation; Computer networks; Design automation; Field programmable gate arrays; Fires; Hardware; Neurons; Physics; Random number generation; Timing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Electronics, 2004. ICSE 2004. IEEE International Conference on

Print_ISBN

0-7803-8658-2

Type

conf

DOI

10.1109/SMELEC.2004.1620858

Filename

1620858