An accurate and fast behavioral model for PLL Frequency Synthesizer phase noise/spurs prediction

Author

Yan, Xiaozhou ; Kuang, Xiaofei ; Wu, Nanjian

Author_Institution

State Key Lab. for Superlattices & Microstructures, Chinese Acad. of Sci., Beijing, China

fYear

2009

Firstpage

223

Lastpage

226

Abstract

This paper presents a behavior model for PLL Frequency Synthesizer. All the noise sources are modeled with noise voltages or currents in time-domain. An accurate VCO noise model is introduced, including both thermal noise and 1/f noise. The behavioral model can be co-simulated with transistor level circuits with fast speed and provides more accurate phase noise and spurs prediction. Comparison shows that simulation results match very well with measurement results.

Keywords

1/f noise; frequency synthesizers; phase locked loops; phase noise; thermal noise; transistors; voltage-controlled oscillators; 1/f noise; PLL frequency synthesizer phase noise prediction; PLL frequency synthesizer phase spurs prediction; VCO noise model; fast behavioral model; phase-locked loop; thermal noise; time-domain currents; time-domain noise voltages; transistor level circuits; Circuit noise; Circuit simulation; Frequency synthesizers; Phase locked loops; Phase noise; Predictive models; Time domain analysis; Voltage; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2009. CICC '09. IEEE

Conference_Location

San Jose, CA

Print_ISBN

978-1-4244-4071-9

Electronic_ISBN

978-1-4244-4073-3

Type

conf

DOI

10.1109/CICC.2009.5280844

Filename

5280844