A digital phase-sensitive detector for electrical impedance tomography

This paper presents a design of a phase-sensitive detector based on matched filter principles and implemented using digital signal processing (DSP) technology for electrical impedance tomography (EIT) system. The digital phase-sensitive detector (DPSD) was realized with DSP, field programmable gate array (FPGA) chips and other analog circuits. The sampling pulse controlling the analog-to-digital converter (ADC) was generated from the FPGA and synchronized with the exciting sine signal produced by the direct digital synthesis (DDS) module implemented in the FPGA. Thus the phase calculated by the DPSD had a real reference. In order to avoid having samples taken at the same phase over multiple cycles, the nonuniform sampling technique was adopted. Measurements on a saline filled tank show that the signal-to-noise ratio (SNR) of the system can be up to 60 dB.