Designing a TCP/IP core for power consumption analysis

Author

Tanamachi, Kenichi ; Inoue, Koji ; Moshnyaga, Vasily G.

Author_Institution

Dept. of Electron. Eng. & Comput. Sci., Fukuoka Univ., Japan

fYear

2004

Firstpage

412

Lastpage

413

Abstract

In this paper, we have introduced our preliminary design results. The goal of our research is to develop fast, low-power TCP/IP hardcore for future pervasive computing. In this evaluation, we have not taken account of switching activity for each node that is one of the most important factors for power consumption. Our on going work is to capture input stream data to real TCP/IP layers in order to improve the accuracy of our measurements.

Keywords

CMOS logic circuits; hardware description languages; large scale integration; logic CAD; logic partitioning; microprocessor chips; system-on-chip; transport protocols; ubiquitous computing; CMOS LSI; CMOS library; RTL design; TCP/IP core design; Verilog-HDL; custom hardware; logic-synthesis; low-power packet processing; module partitioning; network communication; packet header structure; pervasive computing; power consumption analysis; power-aware hardware designs; protocol stack; standard-cell levels; Capacitance; Computer networks; Computer science; Energy consumption; Hardware design languages; High-speed networks; Power engineering and energy; Protocols; TCPIP; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced System Integrated Circuits 2004. Proceedings of 2004 IEEE Asia-Pacific Conference on

Print_ISBN

0-7803-8637-X

Type

conf

DOI

10.1109/APASIC.2004.1349515

Filename

1349515