A 9.43-ENOB 160MS/s 1.2V 65nm CMOS ADC based on multi-stage amplifiers

A 12-bit 1.2 V 160 MS/s pipeline ADC for high-definition video systems is presented. The proposed multipath frequency-compensation technique enables the conventional RNMC-based three-stage amplifier to achieve a stable operation at a sampling rate of 160 MS/s. The measured differential and integral nonlinearities of the prototype ADC implemented in a 65 nm CMOS process are less than 0.69 LSB and 1.00 LSB respectively. The ADC shows a maximum SNDR of 58.5 dB and 53.1 dB and a maximum SFDR of 76.0 dB and 67.8 dB at 160 MS/s and 200 MS/s, respectively. The ADC with an active die area of 0.72 mm² shows a FoM of 0.75 pJ/conv-step at 160 MS/s and 1.2 V.