Title :
Split capacitor DAC mismatch calibration in successive approximation ADC
Author :
Chen, Yanfei ; Zhu, Xiaolei ; Tamura, Hirotaka ; Kibune, Masaya ; Tomita, Yasumoto ; Hamada, Takayuki ; Yoshioka, Masato ; Ishikawa, Kiyoshi ; Takayama, Takeshi ; Ogawa, Junji ; Tsukamoto, Sanroku ; Kuroda, Tadahiro
Author_Institution :
Keio Univ., Yokohama, Japan
Abstract :
A split capacitor DAC calibration method is proposed that a bridge capacitor larger than conventional design allows a tunable capacitor to compensate for mismatch. To guarantee proper calibration, a comparator with digital timing control offset cancellation is proposed. An 8-bit successive approximation ADC with 4b+4b split capacitor DAC calibration has been implemented in 65 nm CMOS, achieving 0.3LSB DNL and INL with 180fF input capacitance.
Keywords :
analogue-digital conversion; calibration; capacitors; digital-analogue conversion; bridge capacitor; digital timing control offset cancellation; guarantee proper calibration; split capacitor DAC mismatch calibration; tunable capacitor; Bridge circuits; Calibration; Capacitance; Capacitors; Digital control; Timing;
Conference_Titel :
Custom Integrated Circuits Conference, 2009. CICC '09. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-4071-9
Electronic_ISBN :
978-1-4244-4073-3
DOI :
10.1109/CICC.2009.5280859
