Title :
A 6b 3GS/s flash ADC with background calibration
Author :
Kijima, Masashi ; Ito, Kenji ; Kamei, Kuniyoshi ; Tsukamoto, Sanroku
Author_Institution :
Fujitsu VLSI Ltd., Kasugai, Japan
Abstract :
A 6b 3GS/s flash ADC is implemented in a 90 nm CMOS process. The proposed ADC is based on an interpolating flash architecture without a T/H. To overcome the offset mismatch among comparators, an interleaved offset-calibration system is applied. Each 1-bit interpolating unit consisting of two preamplifiers and three comparators takes turns at offset calibration in the background. The ADC achieves the ENOB of 5.8 bit at 3GS/s and the ERBW of 500 MHz while consuming 90 mW from a 1.2 V supply. The ADC occupies a 0.28 mm2 area.
Keywords :
CMOS integrated circuits; analogue-digital conversion; CMOS process; background calibration; flash ADC; interleaved offset calibration; interpolating flash architecture; power 90 mW; size 90 nm; voltage 1.2 V; CMOS process; Calibration; Preamplifiers;
Conference_Titel :
Custom Integrated Circuits Conference, 2009. CICC '09. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-4071-9
Electronic_ISBN :
978-1-4244-4073-3
DOI :
10.1109/CICC.2009.5280860
