Title :
Design of a low power CVSL full adder using low-swing technique
Author :
Kang, Jang Hee ; Kim, Jeong Beom
Author_Institution :
Dept. of Electron. Eng., Kangwon Nat. Univ., South Korea
Abstract :
In this paper, we propose a new low-swing CVSL full adder. The circuit provides lower power consumption than previous implementations. We describe an 8 8 parallel multiplier based on this technique. Simulation results comparing the proposed circuit to the previous implementations show its superiority. Power consumption reduction of 13.1% and power-delay-product reduction of 14.2% are achieved. The validity and effectiveness of the proposed circuits are verified through the HSPICE under Hynix 0.35μm standard CMOS process.
Keywords :
CMOS logic circuits; adders; logic design; low-power electronics; multiplying circuits; 0.35 micron; CMOS process; HSPICE; low power CVSL full adder; low-swing full adder; low-swing technique; parallel multiplier; Adders; CMOS digital integrated circuits; Circuit simulation; Digital circuits; Energy consumption; MOS devices; MOSFETs; Portable computers; Very large scale integration; Voltage;
Conference_Titel :
Semiconductor Electronics, 2004. ICSE 2004. IEEE International Conference on
Print_ISBN :
0-7803-8658-2
DOI :
10.1109/SMELEC.2004.1620880
