64-bit prefix adders: Power-efficient topologies and design solutions

Author

Zhou, Ching ; Fleischer, Bruce M. ; Gschwind, Michael ; Puri, Ruchir

Author_Institution

T.J. Watson Res. Center, IBM, Yorktown Heights, NY, USA

fYear

2009

Firstpage

179

Lastpage

182

Abstract

64-bit adders of various prefix algorithms are designed using a novel dataflow synthesis methodology. Our synthesis methodology offers robust adder solutions typically used for high-performance microprocessor needs. We have analyzed the power-performance tradeoffs for a portfolio of popular adder topologies and design styles. In particular, the intrinsically sparser designs in hierarchical prefix scheme are demonstrated to be preferable choices for both high-performance and low-power adder applications.

Keywords

adders; data flow analysis; logic design; low-power electronics; microprocessor chips; 64-bit prefix adders; dataflow synthesis methodology; hierarchical prefix scheme; high-performance microprocessor; intrinsically sparser design; low-power adder application; power-efficient topology; prefix algorithm design; robust adder solution; Algorithm design and analysis; Microprocessors; Portfolios; Robustness; Topology; Circuit Synthesis; Design Automation; Hierarchical Circuit Design; Prefix Adders;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2009. CICC '09. IEEE

Conference_Location

San Jose, CA

Print_ISBN

978-1-4244-4071-9

Electronic_ISBN

978-1-4244-4073-3

Type

conf

DOI

10.1109/CICC.2009.5280873

Filename

5280873