Title :
A 6-bit arbitrary digital noise emulator in 65nm CMOS technology
Author :
Matsuno, Tetsuro ; Fujimoto, Daisuke ; Kosaka, Daisuke ; Hamanishi, Naoyuki ; Tanabe, Ken ; Shiochi, Masazumi ; Nagata, Makoto
Author_Institution :
Dept. of Comput. Sci. & Syst. Eng., Kobe Univ., Kobe, Japan
Abstract :
An arbitrary noise generator (ANG) is based on time-series charging of divided parasitic capacitance (TSDPC) and emulates power supply noise generation in a CMOS digital circuit. A prototype ANG incorporates an array of 32 times 32 6-bit TSDPC cells along with a 128-word vector memory and occupies 2 times 2 mm2 in a 65 nm 1.2 V CMOS technology. Digital noise emulation of functional logic cores such as register arrays and processing elements is demonstrated with chip-level waveform monitoring at power supply, ground, as well as substrate nodes.
Keywords :
CMOS integrated circuits; integrated circuit modelling; integrated circuit noise; low-power electronics; power supply circuits; time series; 6-bit arbitrary digital noise emulator; CMOS digital circuit; CMOS technology; power supply noise generation; size 65 nm; time-series charging of divided parasitic capacitance; voltage 1.2 V; CMOS digital integrated circuits; CMOS memory circuits; CMOS technology; Circuit noise; Digital circuits; Logic arrays; Noise generators; Parasitic capacitance; Power generation; Power supplies;
Conference_Titel :
Custom Integrated Circuits Conference, 2009. CICC '09. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-4071-9
Electronic_ISBN :
978-1-4244-4073-3
DOI :
10.1109/CICC.2009.5280875
