Title :
Embedded high-speed BCH decoder for new-generation NOR flash memories
Author :
Wang, Xueqiang ; Wu, Dong ; Hu, Chaohong ; Pan, Liyang ; Zhou, Runde
Author_Institution :
Inst. of Microelectron., Tsinghua Univ., Beijing, China
Abstract :
A high-speed double-error-correcting (DEC) BCH decoder for new-generation NOR flash memory is presented to improve reliability. To speed up the decoding process, a multiplication-free linear transform is developed to eliminate iterations and divisions in Galois fields. Furthermore, a reverse data-flow analysis (RDFA) and smoothest descent approach are proposed to reduce latency in the bit-parallel Chien search. Based on peripheral 180 nm CMOS process, the whole BCH decoder is designed and the latency is significantly reduced to less than 5 ns.
Keywords :
CMOS logic circuits; Galois fields; NOR circuits; decoding; digital arithmetic; flash memories; CMOS process; Galois field; NOR flash memories; double error correcting BCH decoder; high-speed BCH decoder; multiplication free linear transform; reverse data flow analysis; size 180 nm; smoothest descent; CMOS process; Data analysis; Delay; Flash memory; Galois fields; Iterative decoding;
Conference_Titel :
Custom Integrated Circuits Conference, 2009. CICC '09. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-4071-9
Electronic_ISBN :
978-1-4244-4073-3
DOI :
10.1109/CICC.2009.5280877
