A full chip integrated power and substrate noise analysis framework for mixed-signal SoC design

A fully integrated framework of full-chip power and substrate noise analysis is discussed, featuring description of transistor-level custom circuits as dynamic noise sources, a high capacity solver for chip-level substrate coupling, and noise back annotation flow to transistors of sensitive circuits. Recursive evaluation of power current and operation timing under the presence of dynamic IR drop greatly improves the accuracy of analysis. A 90-nm CMOS chip was examined both by on-chip noise measurements and full-chip noise analysis.