Investigation of robust full adder cell in 16-nm CMOS technology node

This paper investigates the most popular 1-bit CMOS full adder circuits to examine them for robustness and consistency against adverse variations in process parameters using ultra deep submicron technology nodes such as 16-nm. A ±10% variation is applied in an HSPICE environment to the nominal supply voltage of 0.7 V in the standard superthreshold region, to follow projected trends predicted by the International Technology Roadmap for Semiconductors (ITRS) 2009. A realistic environment is thus created using Gaussian variations on various process parameters, while performing Monte Carlo simulations. Standard design metrics are analyzed and the various topologies are compared to find out the one with best relative robustness performances. The designs offering minimum variabilities for different parameters are reported, to aid the designer in selecting the best cells depending on specific requirements.