32Gb/s 28nm CMOS time-interleaved transmitter compatible with NRZ receiver with DFE

Author

Ogata, Y. ; Hidaka, Y. ; Koyanagi, Yoshio ; Akiya, S. ; Terao, Yutaka ; Suzuki, Kenji ; Kashiwa, K. ; Suzuki, M. ; Tamura, H.

Author_Institution

Fujitsu Labs., Kawasaki, Japan

fYear

2013

Firstpage

40

Lastpage

41

Abstract

We demonstrate that a 32Gb/s transmitter with a 4-way interleaved configuration is feasible in 28nm CMOS. A bit in the data stream contributes to a 2UI-wide pulse in the output signal, eliminating the need for 2-to-1 MUXs and enabling the use of quarter-rate clocking. A 4-tap 1UI-spacing FIR filter is implemented in the transmitter to compensate for the signal loss in the signal transmission media. The output signal is compatible with conventional NRZ receivers with a DFE.

Keywords

CMOS integrated circuits; FIR filters; decision feedback equalisers; receivers; transmitters; 4-tap 1UI-spacing FIR filter; 4-way interleaved configuration; CMOS time-interleaved transmitter; DFE; NRZ receiver; bit rate 32 Gbit/s; data stream; quarter-rate clocking; signal loss compensation; signal transmission media; size 28 nm; CMOS integrated circuits; Clocks; Finite impulse response filters; Optical signal processing; Receivers; Transceivers; Transmitters;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

978-1-4673-4515-6

Type

conf

DOI

10.1109/ISSCC.2013.6487628

Filename

6487628