A 0.94mW/Gb/s 22Gb/s 2-tap partial-response DFE receiver in 40nm LP CMOS

A decision-feedback equalizer (DFE) reconstructs the post-cursor inter-symbol interference (ISI) pattern from the detected data sequence and subtracts it from the received signal before detecting the next symbol. Therefore, DFE´s operating speed is fundamentally limited by a 1-unit-interval (UI) feedback loop that is often the critical path in high-speed designs. Partial-response DFE (prDFE) architectures push the feedback loop away from the analog front-end to the post-slicer domain by making redundant decisions, as shown in Fig. 2.8.1(a). Since distinction between post and current data requires a sequential element to prevent a race, a latch overhead exists in the critical path of many prDFE designs [1]. For a 1-tap prDFE, the design in [2] entirely eliminates the sequential element from the critical path leveraging a unique race-free property of 1-tap half-rate prDFE. However, the architecture is not extendable to larger number of taps. For a 2-tap prDFE, overhead of the sequential element is reduced in a quarter-rate architecture. Figure 2.8.1(b) shows the block diagram of a receiver front-end with a shared CTLE, half-rate slicers and a quarter-rate prDFE. The critical path in the quarter-rate implementation is limited by a 2:1 mux delay (T_mux) and a flop setup and clock-to-output overhead (T_FF), as shown in Fig. 2.8.2(a). Assuming T_FF = 2T_mux, the loop delay increases by 200% compared to the absolute minimum for speculation, T_mux. Figure 2.8.2(a) also shows the race that is prevented by employing the sequential elements in a quarter-rate implementation.