Design of a SOC for low cost IC testing

Author

Ali, Liakot ; Sidek, Roslina ; Aris, Ishak ; Wagiran, Rahman ; Ali, Mohd Alauddin Mohd

Author_Institution

Dept. of Electr. & Electron. Eng., Universiti Putra Malaysia, Selangor, Malaysia

fYear

2004

Abstract

This paper presents the design of a SoC for low cost IC testing using verilog HDL. Conventional IC tester, ATE, is based on deterministic algorithm. With the continuous increase of integration densities and complexities in IC technology, ATE reveals serious drawbacks and point towards having a new approach in IC testing for its economic and reliable solution. Recently researchers have shown that dynamic reseeding based mixed-mode (DRM) approach outperforms all other existing test technologies. The SoC is designed implementing the DRM technique. It is capable of testing combinational circuits as well as sequential circuits with scan-path facilities efficiently. It can also be used for testing PCB interconnection faults.

Keywords

automatic test equipment; combinational circuits; design for testability; hardware description languages; integrated circuit testing; logic CAD; sequential circuits; system-on-chip; SOC design; automatic test equipment; combinational circuit testing; deterministic algorithm; dynamic reseeding based mixed-mode approach; low cost integrated circuit testing; sequential circuits; verilog HDL; Circuit faults; Circuit testing; Combinational circuits; Costs; Hardware design languages; Integrated circuit interconnections; Integrated circuit reliability; Integrated circuit testing; Sequential analysis; Sequential circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Electronics, 2004. ICSE 2004. IEEE International Conference on

Print_ISBN

0-7803-8658-2

Type

conf

DOI

10.1109/SMELEC.2004.1620908

Filename

1620908