3.6GHz 16-core SPARC SoC processor in 28nm

Author

Hart, J. ; Butler, S. ; Hoyeol Cho ; Yuefei Ge ; Gruber, G. ; Dawei Huang ; Changku Hwang ; Jian, D. ; Johnson, Tyler ; Konstadinidis, G. ; Kwong, L. ; Masleid, R. ; Nawathe, U. ; Ramachandran, Aditi ; Yongning Sheng ; Shin, Jinuk Luke ; Turullois, S. ; Z

Author_Institution

Oracle, Santa Clara, CA, USA

fYear

2013

Firstpage

48

Lastpage

49

Abstract

The Oracle SPARC T5 [1] processor introduces significant new capabilities in performance, scalability, multi-socket interconnect, power efficiency, and I/O compared to prior CPU generations [2-6]. T5 multiplies T4 [2, 3] performance by doubling the number of core pipes and making a number of architectural improvements in the SoC. A core frequency of 3.6GHz is achieved with enhancements in circuit design, power distribution and clocking coupled with TSMC´s 28nm triple-V_t process. T5 contains 1.5 billion transistors and 13 metal layers.

Keywords

integrated circuit design; system-on-chip; CPU generations; Oracle SPARC SoC processor; TSMC triple-voltage process; circuit design; core pipes; frequency 3.6 GHz; metal layers; multisocket interconnect; power distribution; power efficiency; size 28 nm; transistors; Clocks; Frequency locked loops; Maintenance engineering; Program processors; Solid state circuits; Synchronization; System-on-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

978-1-4673-4515-6

Type

conf

DOI

10.1109/ISSCC.2013.6487631

Filename

6487631