Incorporating boundary-scan and built-in self-test within a VHDL-based ASIC design cycle

Investigates the application of VHDL to as much of the ASIC design cycle as possible, including the incorporation of testability features. The exercise is based around a case-study ASIC design, which forms part of a larger VHDL design project between BAe, and UH. The partners are sharing all results of the exercise, to help them to both specify and implement testable VHDL-based ASIC designs in the future