Emerging standards at ∼10 Gbps for wireline communications and associated integrated circuit design and validation

Author

Li, Mike Peng ; Shumarayev, Sergey

Author_Institution

Altera Corp., San Jose, CA, USA

fYear

2009

Firstpage

105

Lastpage

112

Abstract

We first review the signaling and jitter requirements for emerging high-speed wireline communication standards at ~10 Gbps, including CEI 11G, XLAUI/CAUI, XFI, and SFP+. We then present an FPGA transceiver architecture and subsystem/circuit blocks for clocking and timing generation, transmitter buffer, and receiver CDR and DFE, all designed and manufactured with 40-nm process node. Lastly, we present the signal/jitter transmitter output and receiver-tolerance measurement results at 10.3125 Gbps, with an ultra-low random jitter at ~550 fs.

Keywords

clock and data recovery circuits; decision feedback equalisers; field programmable gate arrays; integrated circuit design; integrated circuit manufacture; jitter; transceivers; CEI 11G; FPGA transceiver architecture; SFP+; XFI; XLAUI/CAUI; associated integrated circuit design; bit rate 10.3125 Gbit/s; high-speed wireline communication standards; receiver CDR; receiver DFE; receiver-tolerance measurement; signal-jitter transmitter output; size 40 nm; timing generation; transmitter buffer; ultra-low random jitter; Clocks; Communication standards; Field programmable gate arrays; Integrated circuit synthesis; Jitter; Manufacturing processes; Timing; Transceivers; Transmitters;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2009. CICC '09. IEEE

Conference_Location

San Jose, CA

Print_ISBN

978-1-4244-4071-9

Electronic_ISBN

978-1-4244-4073-3

Type

conf

DOI

10.1109/CICC.2009.5280896

Filename

5280896