Implementation of BIST in 100 k gate ASICS

When moving to a sea-of-gate technology and higher integration densities for a new generation of systems, higher design productivity in the implementation of testability is a key issue. This was addressed using a `two fold´ approach. Firstly the `paracells´ provided to the designer, and the testability architecture, were modified to simplify the design process, primarily by removing the `tight coupling´ between Design-For-Test (DFT) and functional design which the previous methodology had required. Secondly a `testability advisor´ was developed which gave designers early warning of violation of testability rules and also automatically gave the configuration of loops and LFSRs in order to meet the restrictions imposed by the ICL self-test methodology