A 18mW 10Gbps continuous-time FIR equalizer for wired line data communications in 0.12µm CMOS

This paper presents a 10 Gbps continuous-time FIR receiver equalizer design with a frac14 symbol-period differential self-biased active inductor delay line in 0.12 mum CMOS for wired line data communications. The proposed delay line, together with a proposed active inductor Cherry-Hooper transimpedance load at the FIR filter summing node, increases the equalizer speed, while reducing the equalizer power consumption to only 18 mW. The prototype occupies 0.03 mm² die area and measurement results show that the equalizer can compensate for 15 dB channel loss at 5 GHz for 10 Gbps data transmission.