DocumentCode :
1704029
Title :
A 18mW 10Gbps continuous-time FIR equalizer for wired line data communications in 0.12µm CMOS
Author :
Liu, Hao ; Liu, Jin ; Payne, Robert ; Cantrell, Cy ; Morgan, Mark
Author_Institution :
Univ. of Texas at Dallas, Richardson, TX, USA
fYear :
2009
Firstpage :
113
Lastpage :
116
Abstract :
This paper presents a 10 Gbps continuous-time FIR receiver equalizer design with a frac14 symbol-period differential self-biased active inductor delay line in 0.12 mum CMOS for wired line data communications. The proposed delay line, together with a proposed active inductor Cherry-Hooper transimpedance load at the FIR filter summing node, increases the equalizer speed, while reducing the equalizer power consumption to only 18 mW. The prototype occupies 0.03 mm2 die area and measurement results show that the equalizer can compensate for 15 dB channel loss at 5 GHz for 10 Gbps data transmission.
Keywords :
CMOS integrated circuits; FIR filters; data communication; equalisers; inductors; microwave receivers; CMOS integrated circuit; Cherry-Hooper transimpedance load; FIR filter; bit rate 10 Gbit/s; continuous-time FIR receiver equalizer; data transmission; delay line; differential self-biased active inductor; frequency 5 GHz; loss 15 dB; power 18 mW; size 0.12 mum; wired line data communications; Active inductors; Area measurement; Data communication; Delay lines; Energy consumption; Equalizers; Finite impulse response filter; Loss measurement; Propagation losses; Prototypes;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Custom Integrated Circuits Conference, 2009. CICC '09. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-4071-9
Electronic_ISBN :
978-1-4244-4073-3
Type :
conf
DOI :
10.1109/CICC.2009.5280897
Filename :
5280897
Link To Document :
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