Planning test strategies at board level

Test strategy options have to be examined before the completion of the board development, in order to accommodate possible changes in the board design. This highlight the need for predictive tools to calculate the cost and achievable quality of board test strategies. This work addresses a key area in chip design-test issues typically take up as much time as the functional design, but are often overlooked or underestimated. In addition, given the complexity of the problem, it is very difficult to ensure a high quality and cost effective test. The authors have successfully used economics modelling techniques for ASIC test strategy planning, which have been incorporated in a test advisor system. This submission will provide examples of the use of economics models in the planning of board strategies. The models are fully parameterised and are part of an industrial testability advisor tool, which was developed as part of the ESPRIT EVEREST programme in association with Siemens-Nixdorf in Munich