A 5Gbps 0.13μm CMOS pilot-based clock and data recovery scheme for high-speed links

This paper presents a pilot-based clock and data recovery CDR technique for high-speed serial link applications where a low-amplitude bitrate clock signal, i.e., a pilot, is added to the transmit signal. The clock tone is extracted at the receiver using an injection locked oscillator and is used to drive the receiver front-end samplers. The performance of the CDR technique is demonstrated using a 5 Gbps differential link fabricated in a 0.13 mum IBM CMOS technology. The designed clock and data recovery circuit has an area of 0.171 mm² and consumes 11.75 mA from a 1.5 V supply voltage at 5 Gbps. The recovered clock peak-peak and rms jitter at 5 Gbps are less than 10 ps (5%UI) and 1.6 ps (0.8%UI) respectively with a loop bandwidth of approximately 28 MHz. The proposed technique simplifies the CDR design and provides data and inter-symbol interference (ISI) independent performance with a small ap5% pilot voltage overhead to the transmit signal.