Title :
A recursive switched-capacitor decimation filter design for 0.8 μm CMOS technology
Author :
Baruqui, F.A.P. ; Peraglia, A. ; Mitra, S.K. ; Franca, J.E.
Author_Institution :
Programa de Engenharia Eletrica COPPE, Rio de Janeiro, Brazil
Abstract :
This paper presents the design steps considered in the development of an integrated circuit for a switched-capacitor decimation filter. The design consists of dimensioning the operational amplifiers, capacitances and analog switches, using a supply voltage of 5.5 V for a 0.8 μm technology. Also shown are electrical simulations using PSPICE 5.0 considering both typical and worst case conditions for practical application in telecommunication systems, for a sampling rate reduction from 48.20 MHz to 16.07 MHz. The filter dissipates approximately 46 mW (including the output buffer) at 5.5 V, and presents a flat frequency response within 0.12 dB from dc to 3.56 MHz
Keywords :
CMOS analogue integrated circuits; SPICE; circuit analysis computing; frequency response; recursive filters; switched capacitor filters; 0 to 3.56 MHz; 0.8 micron; 16.07 to 48.20 MHz; 46 mW; 5.5 V; CMOS technology; PSPICE 5.0; analog switches; capacitances; dimensioning; electrical simulations; flat frequency response; output buffer; recursive switched-capacitor decimation filter; sampling rate reduction; supply voltage; telecommunication systems; worst case conditions; Capacitance; Circuit simulation; Filters; Integrated circuit technology; Operational amplifiers; SPICE; Switches; Switching circuits; Telecommunication switching; Voltage;
Conference_Titel :
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-4455-3
DOI :
10.1109/ISCAS.1998.704496
